The present invention relates to a process executing system in which interrupt generating sources of a plurality of peripheral devices, such as the control circuit thereof, are connected to the main process device and, more particularly, to an interrupt control system of the process executing system in which the interrupt signal and the process priority are input from the peripheral device side to the main process device.
Usually, in a processing device such as a main electronic computer, a terminal control apparatus, or a communication control apparatus, a plurality of peripheral devices such as a magnetic disc device, floppy disc device circuit, a keyboard, a console panel, a line printer, a social printer, etc, are connected thereto, and a process is executed between these devices and the processing device, based on an interrupt signal routine.
Further, for the process executed by the processing device, usually a process priority (known as a process level) is previously allocated. When the process levels to which executions are requested collide, the processing device executes a priority sequence in which the process having a high process level in accordance with the process level is given priority.
An input/output process which is based on the interrupt signal mentioned above is set to a level higher than the process level now occupied by a program task, and also is set to a plurality of levels (also known as an interrupt level) which are different in each peripheral device, so that processing of the whole synthetic system proceeds smoothly.
However, in the above-mentioned conventional system, the interrupt lines from each interrupt generating source are individually connected in the so called wired OR manner, that is, fixedly connected to the interrupt signal wires by a bus line, and accordingly, when each system is formed, the connection must be made in the order of the process interrupt priority of each interrupt generating source.
That is, the interrupt priority cannot be changed and, therefore, the general freedom of the system is curtailed.
Further, as each terminal of a plurality of the interrupt generating sources is connected in a straight line, (e.g., an interrupt process at the main CPU) an interrupt (process including a collision process when more than two interrupt signals co-exist at the same terminal), becomes large scale which gives rise to a drawbacks such as creating a large load at the main CPU.